This invention relates to semiconductor devices and methods of manufacture, and more particularly to an insulated gate field effect transistor having a channel stop region.
MOS transistors, particularly N-channel devices, must have "channel stop" regions to prevent the semiconductor material under the field oxide from inverting and forming unwanted transistors. The channel stop regions are usually formed by ion implant before field oxide growth as disclosed in U.S. Pat. No. 4,055,444, issued to G. R. Mohan Rao, assigned to Texas Instruments. The N+ causes high capacitance of the drain or source to channel stop. This capacitance can be a dominant factor in limiting the device speed.
It is the principal object of this invention to provide an improved insulated gate field effect transistor device. Another object is to provide an MOS transistor of small size which has lower source/drain to channel stop capacitance. An additional object is to provide an MOS transistor with channel stop made by a more efficient method. A further object is to provide a higher speed MOS transistor.